This application claims the priority of Korean Patent Application No. 2004-43448, filed on Jun. 14, 2004, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a memory system, and more particularly, to a memory system with a structure that stably terminates a pair of differential signals transmitted via a pair of differential transmission lines in a standby mode.
2. Description of the Related Art
A memory system includes a memory device and a memory controller. The memory device is connected to the memory controller via signal transmission lines. In general, signal transmission lines are terminated at a predetermined voltage for stable transmission of signals.
FIG. 1 illustrates a conventional memory system that performs center tab termination (CTT) on a single-ended signal VSOUT. In the memory system of FIG. 1, a single-ended transmission line 15 is installed between a transmitter 11 and a receiver 13. If the transmitter 11 is a memory device, the receiver 13 is a memory controller, and vice versa. The transmitter 11 outputs the single-ended signal VSOUT to the single-ended transmission line 15, and the receiver 13 receives it via the single-ended signal VSOUT.
In particular, for stable transmission of the single-ended signal VSOUT, an end of a termination resistor RT is connected to the single-ended transmission line 15 and a termination voltage VTT is applied to the other end thereof. During the CTT, the termination voltage VTT is generally maintained at half a power supply voltage applied to the transmitter 11 and the receiver 13.
FIG. 2 illustrates an example of a conventional memory system that performs CTT on a pair of differential signals. In the memory system of FIG. 2, a pair of differential transmission lines 25a and 25b are installed between a transmitter 21 and a receiver 23. When the transmitter 21 is a memory device, the receiver 23 is a memory controller, and vice versa. The transmitter 21 outputs a pair of differential signals VDOUT and /VDOUT to the pair of differential transmission lines 25a and 25b, and the receiver 23 receives it via the pair of differential transmission lines 25a and 25b. 
In particular, for stable transmission of the pair of differential signals VDOUT and /VDOUT, one end of each of termination resistors RT having the same resistance value is connected to one of the pair of differential transmission lines 25a and 25b, and a termination voltage VTT is applied to the other end of the each of the termination resistors RT. As in the memory system of FIG. 1, the termination voltage VTT is maintained to be half a power supply voltage VDDQ applied to the transmitter 21 and the receiver 23.
FIG. 3 illustrates another example of a conventional memory system that performs CTT on a pair of differential signals VDOUT and /VDOUT. In the memory system of FIG. 3, a termination resistor RT is installed between a pair of differential transmission lines 25a and 25b for stable transmission of the pair of differential signals VDOUT and /VDOUT.
As described above, in conventional memory systems, transmission lines are basically terminated at a voltage that is half a power supply voltage VDDQ applied to a transmitter and a receiver during the CTT for stable transmission of signals. Thus, voltages of signals on transmission lines are maintained to be half the power supply voltage VDDQ in a standby mode.
As shown in FIGS. 2 and 3, during the CTT of the pair of differential signals VDOUT and /VDOUT, their voltages are kept to be half the power supply voltage VDDQ, in the standby mode. In this case, it is difficult to determine the exact levels of signals input to the receiver 23. Accordingly, the receiver 23 has difficulty detecting valid transition of the levels of input signals; in particular, when operating frequencies of the input signals are high.